Showing 121–150 of 3345 resultsSorted by latest
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Debugging Techniques in VCS
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Advanced Testbench Using SystemVerilog in VCS
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SystemVerilog for Verification (SV Basics) in VCS
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RTL Compilation & Simulation Setup in VCS
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Testbench Architecture & Verification Methodology
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Introduction to Synopsys VCS & RTL Verification Flow
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ECO Closure & Signoff Flow in PrimeTime
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Power-Aware Timing & Leakage Analysis in PrimeTime
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Signal Integrity & Crosstalk Analysis in PrimeTime
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Advanced STA: OCV, AOCV & POCV Analysis in PrimeTime
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Clock Tree & Uncertainty Analysis in PrimeTime
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Multi-Corner Multi-Mode (MCMM) Analysis in PrimeTime
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Timing Analysis Modes (Setup, Hold & Recovery/Removal) in PrimeTime
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Timing Constraints & SDC Methodology in PrimeTime
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Introduction to Synopsys PrimeTime & STA Fundamentals
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Design Setup & Netlist Integration for STA in PrimeTime
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3DIC Tapeout, Packaging & Manufacturing Closure
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Verification, DRC/LVS & Multi-Die Signoff in 3DIC Compiler
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Power Delivery Network (PDN) in 3D Systems
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3D Routing & Interconnect Optimization in 3DIC Compiler
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Technology Libraries & Process Design Kit (PDK) Setup in Custom Compiler
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Thermal Analysis & Power Integrity in 3DIC Compiler
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3D Floorplanning & Die Stacking Techniques in 3DIC Compiler
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Interposer Design & 2.5D Integration in 3DIC Compiler
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Chiplet-Based Design Integration Flow in 3DIC Compiler
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3DIC Design Planning & Multi-Die Architecture Setup
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3DIC Compiler Fundamentals & Platform Overview
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Custom IC Design Signoff & Tapeout Preparation in Custom Compiler
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Parasitic Extraction & Post-Layout Simulation in Custom Compiler
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Custom Compiler Advanced Layout Techniques
