Description

Introduction

Synopsys Fusion Compiler is a unified RTL-to-GDSII implementation platform. It integrates logic synthesis, floorplanning, placement, routing, and optimization into a single environment. As a result, it enables faster design convergence. Moreover, it combines logical and physical design stages using advanced optimization techniques.

In addition, for floorplanning and power planning, Fusion Compiler offers strong capabilities. These include die and core definition, macro placement, and power grid creation. Furthermore, it supports early-stage physical analysis. Therefore, designers can achieve better performance, improved power efficiency, and optimal area utilization.

Learner Prerequisites

• Basic understanding of digital IC design and VLSI concepts
• Familiarity with ASIC design flow and physical design stages
• Knowledge of standard cells, macros, and technology libraries
• Understanding of timing, power, and area trade-offs
• Basic experience with EDA tools and Linux environment

Table of Contents

1. Floorplanning Fundamentals

1.1 Introduction to Floorplanning Concepts
1.2 Importance of Floorplanning in Physical Design
1.3 Key Objectives: Area, Timing, Power, and Congestion
1.4 Overview of Fusion Compiler Floorplanning Flow
1.5 Design Hierarchy and Block-Level Planning

2. Design Initialization for Floorplanning

2.1 Importing Design and Libraries
2.2 Setting Up Technology and Physical Libraries
2.3 Initial Design Checks and Validation
2.4 Defining Constraints for Floorplanning
2.5 Understanding Design Hierarchy and Partitions

3. Die and Core Area Definition

3.1 Die Size Estimation Techniques
3.2 Core Area and Aspect Ratio Planning
3.3 Utilization and Density Considerations
3.4 IO Placement Strategy and Guidelines
3.5 Pin Assignment and Optimization

4. Macro Placement Strategy

4.1 Types of Macros and Their Characteristics
4.2 Macro Placement Guidelines and Best Practices
4.3 Handling Hard Macros and IP Blocks
4.4 Macro Orientation, Alignment, and Spacing
4.5 Avoiding Congestion and Routing Blockages

5. Floorplan Optimization Techniques

5.1 Congestion Analysis and Mitigation
5.2 Placement Blockages and Keep-out Margins
5.3 Channel Spacing and Routing Considerations
5.4 Hierarchical Floorplanning Approaches
5.5 Iterative Floorplan Refinement

6. Power Planning Fundamentals

6.1 Introduction to Power Distribution Networks (PDN)
6.2 Power Planning Objectives and Challenges
6.3 Overview of Power Domains and Voltage Islands
6.4 UPF/CPF Basics for Power Intent
6.5 IR Drop and EM Considerations

7. Power Grid Design in Fusion Compiler

7.1 Creating Power Rings and Straps
7.2 Power Mesh and Grid Topologies
7.3 Layer Selection and Metal Utilization
7.4 Via Insertion and Connectivity Checks
7.5 Power Grid Verification Techniques

8. Advanced Power Planning Techniques

8.1 Multi-Voltage Design Implementation
8.2 Power Gating and Isolation Strategies
8.3 Decoupling Capacitor Insertion
8.4 Dynamic and Static IR Drop Analysis
8.5 Electromigration Analysis and Fixes

9. Integration of Floorplanning and Power Planning

9.1 Co-optimization of Floorplan and Power Grid
9.2 Impact of Macro Placement on Power Integrity
9.3 Early Timing and Power Analysis
9.4 Iterative Design Refinement
9.5 Design Rule and Signoff Checks

10. Tool Commands and Automation in Fusion Compiler

10.1 Key Floorplanning Commands and Scripts
10.2 Power Planning Command Usage
10.3 Automating Floorplan and PDN Creation
10.4 Debugging and Log Analysis
10.5 Best Practices for Efficient Tool Usage

11. Verification and Signoff Checks

11.1 Design Rule Checks (DRC) for Floorplan
11.2 Layout Versus Schematic (LVS) Basics
11.3 Power Integrity Verification
11.4 Congestion and Timing Validation
11.5 Signoff Criteria and Checklist

12. Real-World Case Studies and Best Practices

12.1 Industry Use Cases for Floorplanning
12.2 Common Challenges and Solutions
12.3 QoR Improvement Techniques
12.4 Debugging Floorplan Issues
12.5 Best Practices for Advanced Nodes

Conclusion

In conclusion, this training provides a complete understanding of floorplanning and power planning in Synopsys Fusion Compiler. Moreover, it helps learners design efficient and high-performance chip layouts. As a result, participants can improve design quality, reduce iterations, and achieve faster convergence in modern semiconductor design flows.