Description

Introduction
Fusion Compiler is an advanced physical implementation solution developed by Synopsys. It unifies synthesis, placement, routing, and optimization into a single platform. As a result, it enables faster design convergence and improves overall performance. In addition, it helps reduce power consumption for complex semiconductor designs. By leveraging a unified data model and AI-driven optimization, Fusion Compiler streamlines the entire RTL-to-GDSII flow efficiently.

Learner Prerequisites

• A basic understanding of VLSI design flow
• Familiarity with digital design concepts and Verilog/SystemVerilog
• Knowledge of synthesis, placement, and routing fundamentals
• Exposure to Linux/Unix environments and command-line usage
• Understanding of timing concepts such as setup, hold, and clock domains

Table of Contents

1. Introduction to Fusion Compiler and Physical Design Flow
1.1 Overview of Physical Design in VLSI
1.2 Evolution from Traditional Flows to Fusion Compiler
1.3 Key Features and Benefits of Fusion Compiler
1.4 Fusion Compiler Architecture and Unified Data Model
1.5 Comparison with Other Implementation Tools
1.6 Understanding RTL-to-GDSII Flow Integration
1.7 Role of Fusion Compiler in Modern Chip Design

2. Fusion Compiler Environment Setup and Tool Navigation
2.1 Installation and Licensing Overview
2.2 Setting Up Environment Variables
2.3 Launching Fusion Compiler GUI and CLI
2.4 Understanding Tool Interface and Layout
2.5 Navigating Design Databases and Libraries
2.6 File Formats and Design Inputs (LEF, DEF, Liberty, Verilog)
2.7 Managing Projects and Workspace Setup
2.8 Introduction to TCL Scripting in Fusion Compiler

3. Design Initialization and Floorplanning Basics
3.1 Importing Design and Library Data
3.2 Design Initialization Flow
3.3 Floorplan Concepts and Core Utilization
3.4 IO Placement and Pin Assignment
3.5 Power Planning and Power Grid Basics
3.6 Macro Placement Strategies
3.7 Constraints Setup and SDC Overview
3.8 Design Rule Constraints and Checks

4. Placement and Optimization Techniques
4.1 Standard Cell Placement Concepts
4.2 Global Placement and Legalization
4.3 Congestion Analysis and Mitigation
4.4 Timing-Driven Placement Optimization
4.5 Power Optimization Techniques
4.6 Handling High Fanout Nets
4.7 Incremental Placement Strategies
4.8 Placement Quality Checks

5. Clock Tree Synthesis (CTS)
5.1 Fundamentals of Clock Tree Design
5.2 Clock Tree Synthesis Flow in Fusion Compiler
5.3 Clock Constraints and Definitions
5.4 Skew, Latency, and Uncertainty Management
5.5 Clock Buffering and Routing Techniques
5.6 CTS Optimization and Debugging
5.7 Multi-Clock Domain Handling

6. Routing and Post-Route Optimization
6.1 Routing Concepts and Types (Global & Detailed Routing)
6.2 Routing Algorithms in Fusion Compiler
6.3 Signal Integrity and Crosstalk Analysis
6.4 Design Rule Checking (DRC) and Fixes
6.5 Post-Route Timing Optimization
6.6 Power and Noise Optimization
6.7 ECO Routing Techniques
6.8 Routing Quality Metrics

7. Timing Analysis and Signoff Preparation
7.1 Static Timing Analysis (STA) Overview
7.2 Setup and Hold Timing Analysis
7.3 Multi-Corner Multi-Mode (MCMM) Analysis
7.4 Timing Reports and Debugging Violations
7.5 Parasitic Extraction Basics
7.6 Signoff Checks and Validation
7.7 Integration with Signoff Tools

8. Power Analysis and Optimization
8.1 Power Components (Dynamic and Leakage)
8.2 Power Estimation Techniques
8.3 Low Power Design Techniques
8.4 Multi-Voltage and Power Domains
8.5 IR Drop and EM Analysis Basics
8.6 Power Optimization Strategies in Fusion Compiler

9. Design Closure and Final Deliverables
9.1 Understanding Design Closure Criteria
9.2 Fixing Timing, DRC, and LVS Issues
9.3 Engineering Change Orders (ECOs)
9.4 Generating GDSII and Final Outputs
9.5 Documentation and Reporting
9.6 Best Practices for Tape-Out

10. Advanced Features and Automation
10.1 AI-Driven Optimization in Fusion Compiler
10.2 Advanced Scripting and Automation Techniques
10.3 Custom Flow Development
10.4 Debugging and Performance Tuning
10.5 Integration with EDA Tool Ecosystem
10.6 Handling Large-Scale Designs

Conclusion
In conclusion, this training provides a comprehensive foundation in Fusion Compiler. It covers everything from tool introduction to design closure. Moreover, learners gain practical insights into modern physical design methodologies. As a result, they can efficiently implement high-performance and low-power chip designs using an industry-leading tool.