Description

Introduction

Synopsys Custom Compiler is a next-generation custom IC design platform used for schematic capture, symbol creation, and hierarchical design management in full-custom, analog, RF, and mixed-signal IC design flows. It provides tight integration with PDKs, simulation environments, and layout tools, enabling a unified design environment from schematic entry to signoff. The tool supports advanced hierarchy handling, reusable design blocks, and efficient library management to improve design scalability and productivity.

Learner Prerequisites

• Basic understanding of analog and digital circuit design concepts
• Familiarity with schematic capture and netlist concepts
• Awareness of CMOS technology and PDK-based design flow
• Basic knowledge of hierarchical design methodology
• Understanding of EDA tool environments and library structures
• Exposure to IC design flow (optional but recommended)

Table of Contents

1. Introduction to Symbol Creation & Hierarchical Design

1.1 Overview of symbol-based schematic design
1.2 Role of hierarchy in complex IC designs
1.3 Importance of modular design methodology

2. Symbol Creation Fundamentals

2.1 Creating new symbols in Custom Compiler
2.2 Mapping symbols to schematic views
2.3 Editing symbol geometry and appearance
2.4 Defining default attributes and parameters

3. Pin Definition and Symbol Properties

3.1 Adding input, output, and bidirectional pins
3.2 Naming conventions and pin ordering standards
3.3 Electrical property assignment to pins
3.4 Managing symbol attributes and metadata

4. Hierarchical Design Management Basics

4.1 Concept of hierarchy in IC design flows
4.2 Top-down vs bottom-up design approaches
4.3 Creating hierarchical blocks and sub-circuits
4.4 Navigating between hierarchy levels

5. Hierarchical Schematics and Block Structuring

5.1 Instantiating symbols in higher-level schematics
5.2 Connecting hierarchical blocks using ports
5.3 Maintaining design consistency across levels
5.4 Managing multiple schematic views

6. Library Management and Design Reuse

6.1 Creating and organizing symbol libraries
6.2 Version control and library updates
6.3 Reusable IP block creation
6.4 Sharing libraries across projects

7. Netlisting and Connectivity Validation

7.1 Generating hierarchical netlists
7.2 Checking connectivity integrity across levels
7.3 Resolving open nets and mismatches
7.4 Netlist export for simulation tools

8. Advanced Hierarchy Operations

8.1 Flattening hierarchical designs
8.2 View binding and view switching
8.3 Parameter propagation across hierarchy
8.4 Managing multi-level design complexity

9. Debugging Symbol and Hierarchy Issues

9.1 Common symbol creation errors
9.2 Hierarchical connectivity troubleshooting
9.3 Pin mismatch and netlist errors
9.4 Debugging using verification tools

10. Best Practices for Scalable Design Hierarchies

10.1 Standard naming conventions for symbols and blocks
10.2 Optimizing hierarchy depth for performance
10.3 Library reuse strategies for large projects
10.4 Design maintainability and documentation practices

Conclusion
Symbol creation and hierarchical design management in Synopsys Custom Compiler form the foundation of scalable and reusable IC design methodologies. Mastering these concepts enables efficient schematic organization, improved design reuse, and streamlined integration across complex analog and mixed-signal projects.