Description

Introduction
Synopsys Custom Compiler is a modern custom IC design platform used for schematic capture, circuit design entry, and full-custom/analog implementation. It provides a unified environment for schematic editing, symbol handling, and tight integration with simulation and layout flows. The tool is widely adopted for analog, RF, mixed-signal, and custom digital block design. It supports advanced PDK integration and efficient design reuse. It enables faster and more accurate design entry for semiconductor workflows.

Learner Prerequisites

• Basic knowledge of CMOS devices and analog/digital circuit fundamentals
• Understanding of semiconductor design flow (RTL-to-GDSII overview)
• Familiarity with schematic concepts and circuit representation
• Awareness of PDKs and technology nodes
• Basic understanding of SPICE simulation concepts

Training Table of Contents

1. Introduction to Schematic Capture in Custom Compiler
1.1 Overview of schematic-driven design flow and its importance
1.2 Role of schematic entry in analog and custom IC design
1.3 Connection between schematic, simulation, and layout
1.4 Benefits of using Custom Compiler for schematic capture
1.5 High-level design flow from schematic to netlist

2. Custom Compiler Environment Overview
2.1 Workspace layout, panels, and project navigation
2.2 Library manager and design database structure
2.3 Schematic editor interface and toolbars
2.4 File management and project organization
2.5 Integration with simulation and verification tools

3. Library and Technology Setup
3.1 PDK integration and technology file configuration
3.2 Loading standard cell and device libraries
3.3 Symbol library organization and mapping
3.4 Cell views and library hierarchy management
3.5 Verifying technology setup correctness

4. Schematic Entry Fundamentals
4.1 Creating new schematic views and design cells
4.2 Placing devices, symbols, and components
4.3 Net creation, wiring, and connectivity rules
4.4 Labeling nets and managing signal flow
4.5 Basic schematic editing operations

5. Device Selection and Parameter Configuration
5.1 Selecting MOSFETs, resistors, capacitors, and inductors
5.2 Defining transistor sizing and model parameters
5.3 Editing properties and device attributes
5.4 Handling process corners and model variations
5.5 Parameter reuse and consistency checks

6. Hierarchical Design Entry
6.1 Creating hierarchical blocks and sub-circuits
6.2 Instantiating modules within top-level schematics
6.3 Managing ports, pins, and interface definitions
6.4 Reusability of hierarchical design blocks
6.5 Debugging hierarchical connectivity issues

7. Electrical Rules and Design Validation
7.1 Running electrical rule checks (ERC)
7.2 Identifying floating nodes and connectivity errors
7.3 Validating schematic correctness before simulation
7.4 Common schematic design rule violations
7.5 Debugging and fixing ERC issues

8. Simulation Preparation and Netlisting
8.1 Generating SPICE netlists from schematic
8.2 Setting up simulation environments and testbenches
8.3 Linking model files and libraries
8.4 Preparing inputs for transient and DC analysis
8.5 Validating netlist accuracy before simulation

9. Advanced Schematic Techniques
9.1 Using parameterized cells (PCells) effectively
9.2 Design reuse strategies for complex circuits
9.3 Handling design variants and configurations
9.4 Managing multi-corner and multi-mode setups
9.5 Optimizing schematic for scalability

10. Design Review and Best Practices
10.1 Improving schematic readability and structure
10.2 Naming conventions and documentation standards
10.3 Hierarchy management for large designs
10.4 Debugging complex schematic issues
10.5 Productivity tips for faster design entry

Conclusion
This training provides a complete foundation in schematic capture and circuit design entry using Synopsys Custom Compiler, enabling learners to build structured, simulation-ready, and reusable analog and custom IC designs efficiently.