Description

Introduction

IC Validator is a high-performance physical verification solution from Synopsys. It is used for signoff-quality checks such as DRC, LVS, and ERC. Moreover, it is widely adopted in advanced semiconductor design flows to ensure design correctness at nanometer and sub-nanometer nodes.

In addition, the tool supports both flat and hierarchical verification methodologies. Therefore, it is highly scalable for modern SoC designs. Furthermore, its distributed processing capabilities and advanced rule handling enable efficient verification of extremely large and complex designs. At the same time, it maintains signoff accuracy and runtime efficiency through tight integration with design flows.

Learner Prerequisites

• Basic understanding of CMOS design rules and VLSI physical design flow
• Familiarity with layout, schematic, and netlist concepts
• Awareness of DRC, LVS, and ERC fundamentals
• Basic Linux and shell command knowledge
• Exposure to EDA tools and physical verification workflows is recommended

Table of Contents

1. Introduction to Hierarchical Verification in IC Validator

1.1 Need for hierarchical verification in large-scale designs
1.2 Flat vs hierarchical verification approaches and trade-offs
1.3 Key challenges in advanced node designs
1.4 Overview of IC Validator hierarchical capabilities
1.5 Signoff flow integration overview

2. Hierarchical Design Data Preparation & Setup

2.1 Design hierarchy understanding (block-level vs top-level)
2.2 LEF/DEF and netlist organization for hierarchical flows
2.3 Library and technology file setup for accurate verification
2.4 Block abstraction and interface definition for modular design
2.5 Runset preparation for hierarchical verification flows

3. Hierarchical DRC Methodology

3.1 Rule checking at block vs top-level implementation
3.2 Distributed DRC execution strategies for performance
3.3 Handling inter-block violations across hierarchy
3.4 Constraint propagation across hierarchical boundaries
3.5 Optimization techniques for runtime reduction

4. Hierarchical LVS Flow & Connectivity Verification

4.1 Netlist partitioning and mapping strategies
4.2 Device matching across hierarchy levels for accuracy
4.3 Pin and port consistency checks for connectivity validation
4.4 Cross-hierarchy connectivity validation techniques
4.5 Debugging LVS mismatches in hierarchical designs

5. Block Abstraction & Model Generation Techniques

5.1 Creating abstract views for IP blocks for reuse
5.2 Black-box vs white-box modeling approaches
5.3 Model accuracy vs performance trade-offs
5.4 Handling encrypted and third-party IP integration
5.5 Reuse strategies for hierarchical verification flows

6. Incremental Verification & ECO Handling

6.1 Change impact analysis in hierarchical designs
6.2 Incremental DRC/LVS runs for ECO cycles
6.3 Localized vs full-chip verification strategies
6.4 ECO validation flow integration for correctness
6.5 Reducing turnaround time during late design stages

7. Debugging & Root Cause Analysis in Hierarchical Flow

7.1 Violation traceability across hierarchy levels
7.2 Debugging connectivity breaks and rule violations
7.3 Using logs and reports effectively for analysis
7.4 Cross-block issue isolation techniques
7.5 Common pitfalls and resolution strategies

8. Advanced Optimization for Large SoC Signoff

8.1 Runtime and memory optimization techniques
8.2 Distributed processing and job parallelization strategies
8.3 Data partitioning strategies for scalability
8.4 Handling ultra-large hierarchical SoC designs
8.5 Best practices for production signoff

Conclusion

This training provides a complete understanding of hierarchical verification methodologies using IC Validator for large-scale and complex SoC designs. In addition, it enables scalable verification strategies that significantly reduce runtime and computational overhead compared to flat flows.

Moreover, the course emphasizes practical techniques such as block abstraction, incremental verification, and ECO handling. Therefore, learners can efficiently manage hierarchical DRC and LVS flows. Ultimately, it helps achieve reliable, signoff-ready results in advanced technology nodes.