Description

Introduction
Fusion Compiler: DFT, Low Power & AI Optimization is based on the advanced RTL-to-GDSII implementation platform Synopsys Fusion Compiler, which integrates synthesis, placement, routing, and optimization in a unified environment. It enables engineers to achieve higher test coverage, optimized power efficiency, and AI-driven design convergence with improved QoR (Quality of Results). This training focuses on DFT methodologies, low power design techniques, AI-based optimization strategies, and implementation flows required for modern semiconductor design.

Learner Prerequisites

• Basic understanding of digital VLSI design flow
• Knowledge of static timing analysis (STA) concepts
• Familiarity with RTL design, synthesis, and physical design stages
• Basic TCL scripting knowledge
• Understanding of DFT concepts (scan, ATPG) is an advantage
• Exposure to low power design methodologies (UPF/CPF) is recommended

Table of Contents

1. Fusion Compiler Overview for DFT, Low Power & AI Optimization
1.1 Introduction to Fusion Compiler Architecture
1.2 Unified RTL-to-GDSII Implementation Flow
1.3 Role of AI in Modern Physical Design

2. Design for Test (DFT) Fundamentals
2.1 DFT Basics and Test Methodologies
2.2 Scan Insertion and Scan Chain Architecture
2.3 Test Compression Techniques and Benefits
2.4 Fault Models and Coverage Analysis

3. ATPG and Test Pattern Generation
3.1 Automatic Test Pattern Generation Overview
3.2 Stuck-at, Transition, and Path Delay Faults
3.3 ATPG Flow Integration in Fusion Compiler
3.4 Test Coverage Improvement Techniques

4. Scan Compression and Test Optimization
4.1 Scan Compression Architecture
4.2 Pattern Reduction Techniques
4.3 Test Cost Reduction Strategies
4.4 Debug and Diagnosis Support

5. Low Power Design Methodologies
5.1 Introduction to Power-Aware Design Flow
5.2 UPF/CPF Power Intent Implementation
5.3 Power Gating and Isolation Strategies
5.4 Multi-Voltage Domain Design

6. Clock and Power Optimization Techniques
6.1 Clock Gating Strategies
6.2 Dynamic and Leakage Power Reduction
6.3 Voltage Scaling Techniques
6.4 Power Optimization in Implementation Flow

7. AI-Driven Placement Optimization
7.1 Machine Learning-Based Placement Techniques
7.2 Congestion Prediction and Reduction
7.3 Timing-Aware Placement Optimization
7.4 QoR Improvement Using AI Engines

8. AI-Based Timing and Convergence Optimization
8.1 Critical Path Prediction Using AI
8.2 Timing Closure Acceleration Techniques
8.3 Iterative Optimization Using ML Models
8.4 Design Convergence Improvements

9. Physical Awareness in DFT and Low Power Flow
9.1 Integration of DFT with Physical Design
9.2 Power-Aware Test Implementation
9.3 Physical Constraints Impact on DFT
9.4 Optimization Across Design Domains

10. Debugging and QoR Analysis
10.1 DFT and Power Issue Debugging
10.2 QoR Metrics Analysis
10.3 Bottleneck Identification Techniques
10.4 Iterative Improvement Methodologies

11. Advanced Optimization and Case Studies
11.1 Full Chip DFT Integration Flow
11.2 Low Power Signoff Scenarios
11.3 AI Optimization Case Study
11.4 End-to-End Implementation Example

Conclusion
This training equips learners with comprehensive knowledge of DFT, low power design, and AI-driven optimization methodologies in Synopsys Fusion Compiler, enabling them to achieve high-quality, power-efficient, and test-robust semiconductor designs ready for advanced silicon implementation.