Description

Introduction

The training on “DRC, LVS & Physical Verification Flow in Custom Compiler” is based on Synopsys Custom Compiler. This advanced tool provides a complete physical design and layout environment. It supports schematic-driven layout creation while also enabling efficient verification and debugging.

Additionally, the platform integrates key verification capabilities within a unified workflow. Therefore, designers can perform analysis and debugging more effectively during layout development.

Learner Prerequisites

• Basic understanding of CMOS fabrication process and layout concepts
• Familiarity with schematic design and netlist generation
• Knowledge of standard cell design and basic physical design flow
• Understanding of DRC, LVS, and parasitic extraction basics
• Exposure to EDA tools and UNIX/Linux environment
• Basic knowledge of Tcl scripting is preferred but not mandatory

Table of Contents

1. Introduction to Physical Verification Flow
1.1 Overview of physical verification in IC design
1.2 Role of DRC, LVS, and ERC in signoff flow
1.3 Industry-standard verification flow stages
1.4 Integration of verification in Custom Compiler environment

2. Overview of Synopsys Custom Compiler for Verification
2.1 Custom Compiler architecture and capabilities
2.2 Layout editing and verification integration
2.3 Technology files and rule decks overview
2.4 Setup of verification environment

3. Design Rule Checking (DRC) Fundamentals
3.1 Introduction to DRC concepts
3.2 Common design rule categories (spacing, width, enclosure)
3.3 Running DRC in Custom Compiler
3.4 Interpreting DRC error markers and reports

4. DRC Debugging and Fix Methodology
3.1 Error classification and prioritization
3.2 Layout correction techniques
3.3 Iterative DRC refinement flow
3.4 Best practices for clean DRC results

5. Layout Versus Schematic (LVS) Fundamentals
5.1 Purpose and importance of LVS
5.2 Netlist extraction and comparison flow
5.3 Device matching principles
5.4 Common LVS mismatch scenarios

6. LVS Execution in Custom Compiler
6.1 Setting up LVS run environment
6.2 Running LVS checks
6.3 Understanding LVS reports
6.4 Debugging opens, shorts, and pin mismatches

7. Parasitic Extraction Overview
7.1 Need for parasitic extraction in verification flow
7.2 RC extraction basics
7.3 Extraction setup in Custom Compiler
7.4 Using extracted data for analysis

8. Physical Verification Signoff Flow
8.1 End-to-end signoff flow explanation
8.2 Interaction between DRC, LVS, and extraction
8.3 Tapeout readiness checklist
8.4 Final signoff closure strategy

9. Advanced Debugging Techniques
9.1 Hierarchical debug methods
9.2 Net tracing and connectivity analysis
9.3 Layout probing tool usage
9.4 Automation to reduce errors

10. Technology Files and Rule Deck Management
10.1 Understanding PDK structure
10.2 Rule deck configuration and updates
10.3 Handling process variations
10.4 Version control for verification decks

11. Automation and Scripting in Verification Flow
11.1 Tcl scripting for batch runs
11.2 Automating DRC and LVS execution
11.3 Log parsing and error reporting
11.4 Improving verification efficiency

12. Case Study: Full Chip Verification Flow
12.1 Block-level verification walkthrough
12.2 Hierarchical LVS and DRC execution
12.3 Debugging real-world design issues
12.4 Final clean signoff flow

Conclusion

This training provides a clear understanding of DRC, LVS, and physical verification flow in Synopsys Custom Compiler. Moreover, it builds strong practical skills in layout verification and debugging. Therefore, learners can confidently handle real-world IC verification tasks.

In addition, the training ensures that designs meet both manufacturing rules and schematic correctness requirements. As a result, learners are well prepared for successful tapeout closure. Furthermore, it strengthens practical decision-making during physical verification workflows.