Introduction

Synopsys Fusion Compiler is an advanced unified RTL-to-GDSII digital implementation tool that integrates synthesis, placement, routing, and optimization into a single environment. It enables efficient design convergence by combining physical and logical optimization engines, supporting high-performance, low-power, and area-optimized semiconductor design. Routing and post-route optimization in Fusion Compiler focuses on completing interconnect planning, reducing congestion, fixing timing violations, and improving overall design quality after detailed routing.

Learner Prerequisites

• Basic understanding of digital VLSI design flow
• Knowledge of timing concepts such as setup and hold
• Familiarity with physical design stages: floorplanning, placement, and routing
• Understanding of standard cell library concepts
• Exposure to RTL design and synthesis tools
• Basic knowledge of Static Timing Analysis (STA)
• Familiarity with TCL scripting fundamentals
• Awareness of EDA tool environments (preferred for hands-on practice)

Table of Contents

1. Routing Fundamentals in Fusion Compiler

1.1 Overview of Global Routing and Detailed Routing
1.2 Routing Architecture and Grid Concepts
1.3 Design Rule Checks (DRC) and Routing Constraints
1.4 Routing Resources, Layers, and Via Strategy
1.5 Congestion-Aware Routing Mechanisms

2. Global Routing Techniques

2.1 Global Route Planning and Estimation
2.2 Congestion Analysis and Visualization
2.3 Net Prioritization and Critical Path Handling
2.4 Layer Assignment Strategies
2.5 Timing-Driven Global Routing Optimization

3. Detailed Routing in Fusion Compiler

3.1 Detailed Router Flow and Algorithms
3.2 Track Assignment and Pin Access Optimization
3.3 Via Insertion and Minimization Techniques
3.4 Short/Open Fixing Mechanisms
3.5 DRC-Compliant Routing Closure Strategies

4. Post-Route Optimization Overview

4.1 Post-Route Optimization Objectives
4.2 Timing Closure after Routing
4.3 Power Optimization Techniques Post Routing
4.4 Area and Wirelength Optimization
4.5 Iterative Refinement Methodologies

5. Timing Fixing After Routing

5.1 Setup and Hold Violation Analysis
5.2 Buffer Insertion and Gate Resizing
5.3 Cell Reordering and Re-structuring
5.4 Clock Tree Impact on Post-Route Timing
5.5 ECO (Engineering Change Order) Flow

6. Signal Integrity and Noise Optimization

6.1 Crosstalk Analysis and Mitigation
6.2 IR Drop Awareness in Routing
6.3 Electromigration Considerations
6.4 Shielding and Spacing Techniques
6.5 Noise-Aware Optimization Strategies

7. Congestion and Design Closure Techniques

7.1 Congestion Detection Post Routing
7.2 Rip-up and Reroute Strategies
7.3 Layer Promotion and Decongestion Methods
7.4 Placement Adjustments for Routing Closure
7.5 Final Design Rule Closure (DRC Fixing)

8. Advanced Post-Route Optimization Techniques

8.1 Machine Learning-Based Optimization in Fusion Compiler
8.2 Multi-Mode Multi-Corner (MMMC) Optimization
8.3 Power Grid Optimization Post Routing
8.4 Design for Manufacturability (DFM) Enhancements
8.5 Signoff Preparation and Quality Checks

Conclusion

This training provides a complete understanding of routing and post-route optimization within Synopsys Fusion Compiler, covering global and detailed routing, timing closure, congestion resolution, and advanced optimization techniques essential for achieving high-quality silicon implementation results.